1. Field of the Invention
The present invention is related to a method and related device of source drivers with reduced power consumption, and more particularly, to a method and related device utilizing a reference voltage source to charge or discharge a loading end of a source driver to a reference voltage.
2. Description of the Prior Art
Recently flat panel display (FPDs) with their flat, thin form factor and high-resolution image quality are getting more and more attention and undergoing explosive growth in the consumer market. The major types of FPDs include plasma display panels (PDP), liquid crystal displays (LCD), and rear projection displays These flat panel displays feature several shared benefits of thin form factor and high-resolution image quality and have already gradually replaced cathode ray tube displays (CRT). Hence, the flat panel displays are widely applied to information products such as notebook computers, personal digital assistants (PDA), flat televisions, and mobile phones.
Please refer to FIG. 1. FIG. 1 is a diagram of a source driver chip 10 utilizing charge sharing in the prior art. The source driver chip 10 includes N channels and is dot inversion. As a result, adjacent operational amplifiers have opposite polarities. For example, the 1st operational amplifier OP+ has a positive polarity, and the 2nd operational amplifier OP− has a negative polarity. Vref[R:1] represents R reference voltages provided to a digital-to-analog converter DAC, and the digital-to-analog converter DAC will subdivide many more voltage levels for usage by the operational amplifiers according to these reference voltages. Code[B:1] is gray-scale digital data desired to be displayed on the flat panel display, and is generated by a timing controller and is transmitted to the source drivers for buffering and usage. Please refer to the 1st channel and the 2nd channel, assuming that all operational amplifiers continuously alternate between a supply voltage AVDD and a grounding voltage GNDA. First, two adjacent loadings Load1 and Load2 outside the source driver chip 10 are shorted when performing charge sharing. At this time, a first switch φ1 is turned on, and the charges of the two loadings Load1 and Load2 outside the source driver chip 10 will redistribute equally, whereof the voltage level after balancing is about one half of the supply voltage AVDD. After that, the first switch φ1 is turned off and an output stage of the operational amplifier is electrically connected to corresponding loading outside the source driver chip 10, for example, the 1st operational amplifier OP+ is coupled to the loading Load1 outside the source driver chip 10 and the 2nd operational amplifier OP− is coupled to the loading Load2 outside the source driver chip 10. At this time, a second switch φ2 is turned on. Hence, the operational amplifier will raise or lower the loading outside the source driver chip 10 to a target voltage (that is the supply voltage AVDD or the grounding voltage GNDA) to accomplish a complete driving operation.
Please refer to FIG. 2, which is a timing diagram of the source driver in FIG. 1. In this embodiment, charge sharing and 1-line dot inversion is adopted. A symbol POL represents a polarity signal of an operational amplifier OP, a symbol LD represents a start signal of the operational amplifier OP, and a symbol OUT represents a voltage level of the loading outside the source driver chip. The polarity of the operational amplifier OP is determined by buffering the polarity signal POL on a rising edge of the start signal LD. As shown in FIG. 2, if the polarity signal POL is buffered as 1 on the rising edge of the start signal LD, the polarity of the operational amplifier OP is a positive polarity. If the polarity signal POL is buffered as 0 on the rising edge of the start signal LD, the polarity of the operational amplifier OP is a negative polarity. During a period that the first switch φ1 is turned on, the loading outside the source driver chip can be raised or lowered to 0.5×AVDD through performing charge sharing. During a period that the second switch φ2 is turned on, the operational amplifier OP is changed to drive the loading outside the source driver chip. At this time, there is still nearly a voltage level of 0.5×AVDD to be driven.
Please refer to FIG. 3. FIG. 3 is another timing diagram of the source driver in FIG. 1. In this embodiment, charge sharing and 2-line dot inversion is adopted. The difference between FIG. 3 and FIG. 2 is that a switch frequency of the operational amplifier OP in FIG. 3 is only one half of the original switch frequency of the operational amplifier OP in FIG. 2. During the period that the first switch φ1 is turned on, the loading outside the source driver chip can be raised or lowered to 0.5×AVDD through performing charge sharing. During the period that the second switch φ2 is turned on, the remnant 0.5×AVDD is driven by the operational amplifier OP. But the polarity is not changed when the first switch φ1 is turned on at the second time until the first switch φ1 is turned on at the third time.
In the source driver architectures utilized in the flat panel displays on hand, charge sharing is adopted to save power consumption. First, two adjacent output ends with opposite polarities are shorted. Until the charges are redistributed equally, the output stages of the source drivers are connected to the output ends to perform charging and discharging on the loadings. The disadvantage of this method is that the loading still has a quite large charging distance to the target voltage after the charges redistribute equally, which will result in wasting much power when the output stage of the source driver charges and discharges the loading.